1. Field of the Invention
The present invention relates to a phase locked loop (PLL) circuit used as a frequency synthesizer, and more particularly, to a PLL circuit that can obtain a stable suppression characteristic of a phase noise in a wide frequency band by preventing the deterioration in phase noise due to a variation in temperature or an individual difference of devices.
2. Description of the Related Art
A frequency synthesizer (hereinafter, referred to as “PLL circuit”) employing a PLL is known as a standard signal generator.
The PLL circuit is widely used in base stations for mobile communication or ground digital broadcast, and requires a low and stable phase noise characteristic to reduce interference with the adjacent carriers by narrowing frequency intervals at the time of arranging carriers.
For example, in an OFDM (Orthogonal Frequency Division Multiplexing) method, wideband signals are transmitted using plural sub carriers orthogonal to each other. Accordingly, the deterioration in phase noise characteristic of an OFDM signal causes the frequency unstable and thus the orthogonality of the sub carriers is damaged, thereby not identifying the carriers.
A conventional PLL circuit is described now with reference to FIG. 7. FIG. 7 is a block diagram schematically illustrating a configuration of the conventional PLL circuit.
As shown in FIG. 7, the conventional PLL circuit includes a voltage controlled oscillator (VCO) 1 oscillating a frequency corresponding to a control voltage, a 1/N frequency divider 2 dividing an output frequency of the VCO 1 by 1/N, an A/D converter 3 converting the divided frequency in a A/D (Analog/Digital) conversion manner, a reference oscillator 5 oscillating a reference frequency, a phase comparator 4 comparing the reference frequency with the output of the A/D converter 3, a digital filter 10′ as a loop filter integrating a phase difference with respect to time by the use of an integration circuit and outputting a pulse as a control voltage value, a D/A converter 8 converting the control voltage value in a D/A (Digital/Analog) conversion manner, and an analog filter 9 smoothing a signal and outputting a control voltage.
The phase comparator 4 is usually embodied by a PLL IC. A counter is usually used as the frequency divider 2.
In the PLL circuit having the above-mentioned configuration, the oscillation frequency output from the VCO 1 is branched and divided by 1/N by the 1/N frequency divider 2, the divided frequency is converted into a digital signal by the A/D converter 3, and then the digital signal is compared in phase with the reference frequency from the reference oscillator 5 by the phase comparator 4, thereby outputting a phase difference.
The detected phase difference is integrated with respect to a constant time by the digital filter 10′ to output an integrated value, the integrated value is converted into an analog signal by the D/A converter 8, the analog signal is smoothed by the analog filter 9 to generated the control voltage, and then the control voltage is sent to the VCO 1. The VCO 1 oscillates a frequency corresponding to the input control voltage. In this way, the PLL circuit performs a feedback control operation of matching the phase of the oscillation frequency of the VCO 1 with the phase of the reference frequency.
In general, the natural frequency fN of the PLL circuit is obtained as fN=(√K0)/2π. Here, K0 represents a loop gain. In the phase noise characteristic, a desired amount of suppressed phase noise is obtained by optimizing the loop gain.
Parameters influencing the loop gain are shown in (1) to (4) of FIG. 7, where four parameters of (1) Kp: phase detection conversion gain, (2) A(s): loop filter transfer function, (3) B: weight by bit in the output of the D/A converter 8, and (4) Kv: VCO conversion gain (VF sensitivity) are shown.
The values of the parameters are calculated by the following expressions:
(1) Kp=(2πA02/fs×N)fs×/2π [V/radian]
(2) A(s)=fs/NL [V/V]
(3) B is (the output voltage amplitude of the D/A converter 8)/(the number of bits)
(4) Kv is a specific value of the VCO [Hz/V]
Here, A0 is a half of the amplitude of I and Q signals orthogonally detected, fs is a sampling frequency, N is a frequency division ratio of the frequency divider 2, and NL is a frequency division ratio at the time of integration.
                The loop gain K0 is calculated by multiplying the parameters of (1) to (4) shown in FIG. 7.        
That is, K0=(1)×(2)×(3)×(4)=Kp×A(s)×B×Kv is calculated. As a result, K0 becomes constant and the amount of suppressed phase noise becomes constant.
As a conventional PLL circuit, “Phase Locked Loop Circuit and Clock Generating Circuit” (applicant: NEC corporation, inventor: Shigesane NOGUCHI) is described in Japanese Unexamined Patent Application Publication No. 2003-168975, published on Jun. 13, H15 (see Patent Document 1).
This conventional PLL circuit is a PLL circuit and a clock generating circuit, which includes a first control loop employing an analog phase comparator and controlling the oscillation on the basis of a phase difference output and a second control loop being oscillated and controlled in accordance with a signal of which a component of the phase difference output in the vicinity of a DC component is enhanced and performing a control operation as a speed lower than that of the first control loop. Accordingly, it is possible to enhance the jitter resistance by suppressing the jitter while enlarging the lock range.
As another PLL circuit, “Fractional-N Phase Locked Loop Frequency Synthesizer” (applicant: Mitsubishi Electric Corporation, inventor: Kenichi TAZIMA) is disclosed in Japanese Unexamined Patent Application Publication No. 2005-33581, published on February 3, H17 (see Patent Document 2).
This conventional PLL circuit is a fractional-N PLL frequency synthesizer in which a feedback circuit generating a synchronization signal from a high-frequency signal of a voltage controlled oscillator includes plural variable frequency dividers dividing a high-frequency signal and outputting a synchronization signal and a modulation circuit outputting control signals of the variable frequency dividers in response to a clock signal in correspondence to the variable frequency dividers. Accordingly, it is possible to perform a high-speed and stable operation.
Patent Document 1: Japanese Unexamined Patent Application Publication No. 2003-168975 (see pages 4 to 7 and FIG. 1)
Patent Document 2: Japanese Unexamined Patent Application Publication No. 2005-33581 (see pages 4 to 7 and FIG. 1)
However, The conventional PLL circuits have a problem that the suppression characteristic of suppressing a phase noise is easily affected by the ambient temperature and a stable suppression characteristic cannot be obtained in an installation place having a great variation in temperature.
The conventional PLL circuits have a problem that the suppression characteristic is also affected by differences in characteristic of components of the PLL circuit, thereby causing individual differences by devices.
The conventional PLL circuits also have a problem that it is difficult to obtain a stable suppression characteristic in a wide frequency band.